A 0.18-ns Response Time Digital LDO Regulator with Adaptive PI Controller in 180-nm CMOS

Digital low drop-out regulator (D-LDO) with fast settling time and superior transient response is gaining increasing attention to make up for the deficiency of analog LDO. However, as traditional digital LDOs regulate output voltage code at a rate 1 bit per clock cycle, speed limited. In this paper, multi-bit conversion technique proposed improve speed. The achieved by an error detector adaptive regulation proportion integration parameters in controller before pass devices. Besides, sensor time-to-digital converter are employed convert codes. Implemented 180-nm CMOS process, D-LDO features under 36/33 mV undershoot/overshoot VOUT = 0.95 V load current steps 40 mA/1 ns on 0.5 nF capacitor. simulated 0.18-ns, figure-of-merit FOM1 0.65 ps FOM2 achieves 0.068 pF.